A MESFET Variable-Capacitance Model for GaAs Integrated Circuit Simulation

Abstract

A simple MESFET capacitance model which has a clearly explained physical meaning for a wide bias voltage range has been developed for use in simulations of GaAs integrated circuits. In this model, gate-source, gate-drain capacitances are represented by analytical expressions which are classified into three different regions for bias voltages: a before-pinch-off region including the neighborhood of the built-in voltage, an after-pinch-off region, a transition region. 2-dimensional analysis results support the validity of the analytically derived capacitance model. The model is applicable to MESFET's used in integrated circuits that have low donor-thickness product.