Band-Engineered Low PMOS V<inf>T</inf> with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Abstract

Using strained SiGe on Si, the threshold voltage of high κ PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high κ and metal gates for 32nm node and beyond.