Through silicon via copper electrodeposition for 3D integration

Abstract

Increasing demands for electronic devices with superior performance and functionality while reducing their sizes and weight has driven the semiconductor industry to develop more advanced packaging technologies. Among all different types of packaging technologies proposed, three-dimensional (3D) vertical integration using through silicon via (TSV) copper interconnect is currently considered one of the most advanced technologies in the semiconductor industry. This paper describes the different materials and processes applied for TSV, with focus on copper electrodeposition, the advantages as well as difficulties associated with this technology and approaches taken to overcome them. The effect of wafer design on process performance and throughput, including necessary process optimizations that are required for achieving void-free via filling while reducing the processing time, will be discussed.