Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

Abstract

For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of stacked chip type 3-D SiP with vertically interconnected TSV are reported. The process includes; 55μm-diameter via holes by reactive ion etching (RIE), SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric layer by thermal oxidation, Ta and Cu seed layers by ionized metal plasma (IMP), Cu via filling by electroplating, Cu/Sn bump for multi-chip stacking and finally chip-to-PCB bonding with Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP with 10 stacked chips was successfully fabricated. High frequency electrical model of the TSV was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. And then, contact resistances of Cu via and bump joint were discussed.