TSV interposer fabrication for 3D IC packaging

Abstract

In this paper, through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200 um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.