Liao Ebin - Concepedia

Author

Liao Ebin

Institute of Microelectronics

Also Known As

Ebin Liao, L Ebin, Liao Ebin

Publications

386

Citations

H-Index

Concepts

All Affiliations

Institute of Microelectronics Nanyang Technological University Agency for Science, Technology and Research Singapore Science Park

About

Liao Ebin is an author at Institute of Microelectronics specializing in engineering, electronic packaging, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	343
2	Electrical Engineering	9	9	313
3	Applied Physics	7	7	163
4	Materials Engineering	2	2	67
5	Computer Engineering	1	1	78

Liao Ebin

Publications

343

Citations

H-Index

Page 1

	Year	Citations
Development of 3D silicon module with TSV for system in packaging Navas Khan, Vempati Srinivasa Rao, Samule Lim, Advanced Packaging3D Ic ArchitectureElectrical EngineeringChip-scale PackageEngineering	2008	78
TSV interposer fabrication for 3D IC packaging Vempati Srinivasa Rao, Ho Soon Wee, Lee Wen Sheng Vincent, EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Stack PackagingWafer Scale Processing	2009	61
Development of dual-etch via tapering process for through-silicon interconnection Ranganathan Nagarajan, Krishnamachar Prasad, Liao Ebin, Sensors and Actuators A Physical Electrical EngineeringEngineeringAdvanced Packaging (Semiconductors)MicrofabricationElectronic Packaging	2007	41
Development of a Novel Deep Silicon Tapered Via Etch Process for Through-Silicon Interconnection in 3D Integrated Systems R. Nagarajan, Liao Ebin, Lee Dayong, EngineeringEtch ThroughputSilicon On InsulatorCopper Diffusion BarrierThrough-silicon Interconnection	2006	37
The development of a tapered silicon micro-micromachining process for 3D microsystems packaging N. Ranganathan, D Y Lee, Liao Ebin, Journal of Micromechanics and Microengineering EngineeringProfile AngleMechanical EngineeringIntegrated CircuitsSilicon On Insulator	2008	33
Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking Won Kyoung Choi, C.S. Premachandran, Ong Siong Chiew, EngineeringInterconnect (Integrated Circuits)Thin Film IndiumLow TemperatureStructural Materials	2009	30
Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication N. Ranganathan, Liao Ebin, Linn Linn, IEEE Transactions on Advanced Packaging EngineeringIntegrated CircuitsSilicon On InsulatorInterconnect (Integrated Circuits)Wafer Scale Processing	2009	21
Fabrication of patterned and non-patterned metallic nanowire arrays on silicon substrate Gaurav Sharma, Ser Choong Chong, Liao Ebin, Thin Solid Films Materials ScienceElectrical EngineeringEngineeringMicrofabricationNanoelectronics	2006	18
Integration of high aspect ratio tapered silicon via for through-silicon interconnection N. Ranganathan, Liao Ebin, Linn Linn, EngineeringSilicon On InsulatorThrough-silicon InterconnectionWafer Scale ProcessingAdvanced Packaging (Semiconductors)	2008	13
Patterned micropads made of copper nanowires on silicon substrate for application as chip to substrate interconnects Gaurav Sharma, C S Chong, Liao Ebin, Nanotechnology EngineeringNanodevicesWafer Scale ProcessingNanoengineeringMaterials Fabrication	2007	11

Page 1