The development of a tapered silicon micro-micromachining process for 3D microsystems packaging

Abstract

It has been shown that as the aspect ratio of through-silicon vias (TSV) increases, tapering of TSV structure greatly helps in achieving good sidewall coverage for dielectric, barrier and copper seed metal layers to eventually achieve a void-free copper via-filling by electroplating process. In the present work, a novel three-step tapered via etching process has been developed and demonstrated as a viable process for fabricating a void-free through-silicon copper interconnection structure. This paper discusses in great detail about the plasma etch mechanisms responsible for the step-by-step evolution of tapered silicon via the profile angle in the desirable range of 83–87°. It is further shown that the above multi-step etch process enables the formation of void-free copper vias for via depths close to 300 µm.