IEEE Transactions on Nuclear Science · 2011 · 97 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsSemiconductor DevicesCombinational Logic DescriptionDigital Logic DesignDynamic Power ReductionMixed-signal IntegrationPhysical DesignArea-efficient Logic Block DesignCombinational Circuit OptimizationCombinational Logic DesignLogic Block DesignLogic OptimizationSingle Event EffectsTransient Fault MitigationTransient Pulse Analysis
A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells.
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