Energy Model of Networks-on-Chip and a Bus

Abstract

A network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-processor system-on-chip (MPSoC) architectures. In earlier papers we proposed two network-on-chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.