Networks on chips: a new SoC paradigm

TLDR

On‑chip micronetworks using a layered methodology are needed to reliably interconnect system‑on‑chip components and meet the design challenges of telecommunications, multimedia, and consumer electronics, where rapid time‑to‑market and plug‑and‑play integration are critical. Focusing on probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. The approach combines deterministic and stochastic models with a modular, component‑based hardware and software design to create complex SoCs. The authors contend that developers will overcome SoC network design challenges and that a layered micronetwork methodology will be essential for mastering future SoC complexity.

Abstract

On-chip micronetworks, designed with a layered methodology, will meet the distinctive challenges of providing functionally correct, reliable operation of interacting system-on-chip components. A system on chip (SoC) can provide an integrated solution to challenging design problems in the telecommunications, multimedia, and consumer electronics domains. Much of the progress in these fields hinges on the designers' ability to conceive complex electronic engines under strong time-to-market pressure. Success will require using appropriate design and process technologies, as well as interconnecting existing components reliably in a plug-and-play fashion. Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies. Overall, these designs will be based on both deterministic and stochastic models. Creating complex SoCs requires a modular, component-based approach to both hardware and software design. Despite numerous challenges, the authors believe that developers will solve the problems of designing SoC networks. At the same time, they believe that a layered micronetwork design methodology will likely be the only path to mastering the complexity of future SoC designs.