Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

TLDR

Off‑state leakage currents in sub‑100 nm CMOS technology have been studied to understand scaling effects. The study examines conventional short‑channel leakage and gate‑oxide leakage in ultrathin‑oxide CMOS devices. Gate‑oxide leakage increases off‑state power by involving more transistors and boosting drain‑side current, yet remains within National Technology Roadmap limits for 1.4–1.5 nm oxides; however, low‑power and memory designs may require 1.8–2.0 nm oxides, indicating that reliability will constrain scaling for high‑performance devices while gate leakage will limit low‑power applications.

Abstract

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.