A 32nm SRAM design for low power and high stability

Abstract

A SRAM cell must meet stringent requirements for operation in the sub-micron/nano ranges. A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability, power dissipation and performance compared with previous designs for low-power memory operation. Initially, this paper presents the optimal transistor sizing for this 9T SRAM cell considering stability, energy consumption, and delay. A write bitline balancing scheme is proposed to reduce the leakage current of the SRAM cell. By optimizing size and employing the proposed write circuitry scheme, a saving of 32% in power dissipation is achieved in memory array operation compared with a conventional 6T SRAM based design. The impact of process variations is investigated in detail, and the HSPICE simulation shows that the 9T SRAM cell has an excellent tolerance to process variations.