IEEE Journal of Solid-State Circuits · 1991 · 18 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignConfigurable Logic BlocksLow-power Digital Circuit DesignMemory DevicesBicmos TechnologyCmos Logic CircuitsLevel Shifter DesignMemory Circuit DesignRedundancy ReductionSense Amplifier DesignSige Bicmos DesignStatic Random-access Memory Design
A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 mu m BiCMOS process. An improved buffer with a high-level output of nearly V/sub CC/ is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the *1 output, having the same critical path as the *4 output circuit, allows for the same access time between the two modes. The *1 or *4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the * mode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size
Hoang Vinh Tran, K. Fung, David A. Bell et al. · 2003 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +15
A 14-ns 1-Mbit CMOS SRAM with variable bit organization
Y. Kohno, T. Wada, Keiko Anami et al. · IEEE Journal of Solid-State Circuits · 1988 · 26 citations
Engineering, Computer Engineering, Electrical Engineering +16