S. Kayano

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

Masahiko Yoshimoto, Keiko Anami, Hirofumi Shinohara et al. · IEEE Journal of Solid-State Circuits · 1983 · 167 citations

Engineering, Computer Engineering, Electrical Engineering +13

A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture

Yutaka Arima, K. Mashiko, Keisuke Okada et al. · IEEE Journal of Solid-State Circuits · 1991 · 54 citations

Engineering, Computer Engineering, Computer Science +15

A 64Kb full CMOS RAM with divided word line structure

Masahiko Yoshimoto, Keiko Anami, Hirofumi Shinohara et al. · 1983 · 46 citations

Engineering, Computer Engineering, Electrical Engineering +14

A self-learning neural network chip with 125 neurons and 10 K self-organization synapses

Yutaka Arima, K. Mashiko, Keisuke Okada et al. · IEEE Journal of Solid-State Circuits · 1991 · 29 citations

Engineering, Computer Engineering, Electrical Engineering +11

An Evaluation of I/sub DDQ/ Versus Conventional Testing for CMOS Sea-of-Gate IC's

Ken Sawada, S. Kayano · 1992 · 28 citations

Engineering, Electrical Engineering, Semiconductor Devices +1