An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

Abstract

A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time. The configurable memory array size architecture allows for memory sizes from 64 kb up to 1 Mb in 64 kb increments with no change in the peripheral circuits. The six-transistor cell layout is shown, and the memory block architecture is illustrated. The low dependence of power supply current on the operating frequency shows the impact of ECL circuits in the design. Characteristics of the SRAM are summarized.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>