A DLL-Based Programmable Clock Multiplier in 0.18-$\mu$m CMOS With ${-}$70 dBc Reference Spur

Abstract

This paper describes a 150-400 MHz programmable clock multiplier which uses a recirculating DLL. The clock multiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18-mum CMOS, consumes 16 mW of power, and achieves 1-5 ps RMS jitter and -70 dBc reference spur level.