IEEE Journal of Solid-State Circuits · 1999 · 1K citations · 20 references
EngineeringElectrical EngineeringCircuit TheoryLow-power DesignMicroelectronicsClock ManagementJitter AnalysisLow-noise Circuit DesignNoiseNoise In Electronic DevicesOscillatorsClock JitterClock Jitter AnalysisLow-noise DesignNoise AnalysisOscillator Noise AnalysisPhase NoisePhase Noise AnalysisRing Oscillators
The paper analyzes clock jitter and phase noise in single‑ended and differential ring oscillators. The authors use impulse sensitivity functions to derive jitter and phase‑noise expressions and analyze how stage count, power, frequency, short‑channel effects, substrate and supply noise, and symmetry influence these metrics. The study provides new design insights for low jitter/phase‑noise ring oscillators and confirms theoretical predictions with experimental measurements.
A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.
20