Demonstration of $L_{g} \sim \hbox{55}\ \hbox{nm}$ pMOSFETs With $\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}$ Channels, High $I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})$ , and Controlled Short Channel Effects (SCEs)

Abstract

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ) devices demonstrate not only controlled short channel effects, but also an excellent on-off current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) ratio (~5times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> 55-nm <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ). The intrinsic gate delay of these heterostructures is ~3 ps at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> . OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.