Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

Abstract

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBM's 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.