The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay

Abstract

There are two major issues in the delay chain based FPGA TDC due to uneven internal delay in the carry chain. (1) The bin widths are uneven and depend on temperature and power supply voltage, which must be calibrated as frequently as possible. The auto-calibration functional block developed in this work provides semi-continuous calibration that converts the TDC measurements from bins to picoseconds. (2) In many applications, the TDC resolution is limited by the “ultra-wide bins”, corresponding to the carry chain crossing at the boundaries of the logic array blocks. The apparent widths of these ultra-wide bins can be several times bigger than the average bin width. The “wave union launchers” described in this paper are designed to make multiple measurements with a single delay chain structure, effectively to sub-divide the ultra-wide bins in each raw measurement. Several TDC schemes with resolutions in 20 to10 picoseconds range implemented in today’s low cost FPGA have been tested.