R. Szplet - Concepedia

Author

R. Szplet

Military University of Technology in Warsaw ORCID

Also Known As

R Szplet, R. Szplet, Ryszard SZPLET, Ryszard Szplet, Szplet Ryszard, Szplet, Ryszard

Publications

1.2K

Citations

H-Index

Concepts

All Affiliations

Military University of Technology in Warsaw

About

R. Szplet is an author at Military University of Technology in Warsaw specializing in computer engineering, engineering, and signal processing.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	16	19	801
2	Computer Engineering	16	20	926
3	Education	7	7	344
4	Computer Science	3	3	117
5	Data Science	1	1	14

R. Szplet

Publications

1.1K

Citations

H-Index

Page 1

	Year	Citations
Field-programmable-gate-array-based time-to-digital converter with 200-ps resolution J. Kalisz, R. Szplet, J. Pasierbinski, IEEE Transactions on Instrumentation and Measurement Electrical EngineeringEngineeringVlsi DesignField-programmable-gate-array-based Time-to-digital ConverterData Converter	1997	164
Interpolating time counter with 100 ps resolution on a single FPGA device R. Szplet, J. Kalisz, R. Szymanowski IEEE Transactions on Instrumentation and Measurement Time CounterAnalog-to-digital ConverterClock RecoveryTiming AnalysisComputer Engineering	2000	127
A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines R. Szplet, Z. Jachna, Paweł Kwiatkowski, Measurement Science and Technology EngineeringMeasurementVideo Coding FormatComputer ArchitectureEducation	2013	86
Single-chip interpolating time counter with 200-ps resolution and 43-s range J. Kalisz, R. Szplet, A. Poniecki IEEE Transactions on Instrumentation and Measurement EngineeringMeasurementFrequency MeasurementComputer ArchitectureEducation	1997	85
An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking R. Szplet, K. Klepacki IEEE Transactions on Instrumentation and Measurement Cyclic PulseElectrical EngineeringPulse ShrinkingEngineeringClock Recovery	2009	75
Nonlinearity correction of the integrated time-to-digital converter with direct coding J. Kalisz, R. Szplet IEEE Transactions on Instrumentation and Measurement Nonlinear System IdentificationNonlinearity CorrectionEngineeringNonlinear CircuitNonlinearity Error	1997	62
Efficient Implementation of Multiple Time Coding Lines-Based TDC in an FPGA Device Paweł Kwiatkowski, R. Szplet IEEE Transactions on Instrumentation and Measurement	2020	58
A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device R. Szplet, J. Kalisz, Z. Jachna Measurement Science and Technology EngineeringMeasurementEducationPs RmsClock Synchronization	2009	44
An Eight-Channel 4.5-ps Precision Timestamps-Based Time Interval Counter in FPGA Chip R. Szplet, Paweł Kwiatkowski, Z. Jachna, IEEE Transactions on Instrumentation and Measurement High ResolutionEngineeringMeasurementReal-time System DesignHardware Algorithm	2016	44
Measurement Uncertainty of Precise Interpolating Time Counters R. Szplet, R. Szymanowski, Dominik Sondej IEEE Transactions on Instrumentation and Measurement EngineeringMeasurementAccuracy And PrecisionEducationClock Synchronization	2019	38

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