A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Abstract

The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 mu A is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4*32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>