IEEE Journal of Solid-State Circuits · 1990 · 13 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsDynamic Power ReductionLow-power Cache DesignMemory DevicesMemory Subsystem DesignPower ManagementPower OptimizationData RetentionEnergy-efficient Memory DesignMemory Array ArchitectureMemory Circuit DesignMemory Power ManagementNon-volatile Memory DesignPower ConsumptionPower-efficient Memory Design
The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 mu A is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4*32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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A 1.5-V DRAM for battery-based applications
Masakazu Aoki, J. Etoh, K. Itoh et al. · IEEE Journal of Solid-State Circuits · 1989 · 36 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 20ns static column 1Mb DRAM in CMOS technology
K. Satō, H. Kawamoto, Kazumasa Yanagisawa et al. · 1985 · 27 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 90ns 4Mb DRAM in a 300 mil DIP
K. Mashiko, M. Nagatomo, Kazutami Arimoto et al. · 1987 · 14 citations
Engineering, Computer Engineering, Electrical Engineering +11
K. Nogami, T. Sakurai, K. Sawada et al. · IEEE Journal of Solid-State Circuits · 1986 · 11 citations
Engineering, Computer Engineering, Electrical Engineering +17