IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009 · 33 citations · 21 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSystem-on-chip DesignChip PackagingDevice ModelingIntegrated Circuit DesignIntegrated Circuit DevicesInterconnect DesignVery-large-scale Integration LayoutElectric Field Integral EquationElectrical Interconnect DesignInterconnect Inductance ModelingInterconnect ModelingInterconnect Resistance ModelingPackage ModelingThree-dimensional Integrated Circuit LayoutThree-dimensional Integration
For the successful electrical design of system-in-package, this paper proposes an efficient method for extracting wideband resistance and inductance from a large number of 3-D interconnections. The proposed method uses the modal equivalent network from the electric field integral equation with cylindrical conduction-mode basis function, which reduces the matrix size for large 3-D interconnection problems. Additional enhancement schemes proposed further reduce the cost for computing the partial inductances. Therefore, the method discussed in this paper can be used to construct accurate models of a large number of 3-D interconnection structures such as more than 100 bonding wires used for stacking chips.
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Numerical Recipes in C: The Art of Scientific Computing.
Chris Birchenhall, William H. Press, Saul A. Teukolsky et al. · The Economic Journal · 1994 · 4.4K citations