Interconnect Inductance Modeling is a computational modeling technique that characterizes the parasitic inductance of on-chip interconnects to enable accurate prediction and analysis of electromagnetic effects in high-speed integrated circuit design.
348
Publications
17.2K
Citations
868
Authors
259
Institutions
Publications per year
2017–2026
25
Parents
Publications
348
1–5 of 348
Authors
868
- EG
12
h-index
- JW
11
h-index
- JLJames L. Drewniak
Missouri University of Science and Technology, United States
11 publications · 402 citations
11
h-index
- JF
10
h-index
- MK
9
h-index
1–5 of 868
Institutions
259
Massachusetts Institute of Technology
Cambridge, United States
15 h-index
51 publications
1.8K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
15 h-index
50 publications
4.2K citations
IBM (United States)
Armonk, United States
14 h-index
32 publications
2.4K citations
University of Rochester
Rochester, United States
13 h-index
30 publications
1.9K citations
Missouri University of Science and Technology
Rolla, United States
12 h-index
49 publications
1.9K citations
Georgia Institute of Technology
Atlanta, United States
12 h-index
53 publications
1.7K citations
Carnegie Mellon University
Pittsburgh, United States
12 h-index
25 publications
923 citations
University of Illinois Urbana-Champaign
Urbana, United States
10 h-index
24 publications
1.6K citations
1–8 of 259
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
17 publications · 1.1K citations
15
h-index
- IEEE Transactions on Microwave Theory and Techniques
15 publications · 728 citations
14
h-index
- IEEE Transactions on Electron Devices
13 publications · 1.6K citations
13
h-index
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
11 publications · 498 citations
11
h-index
- IEEE Transactions on Advanced Packaging
9 publications · 376 citations
9
h-index
1–5