Defect-based delay testing of resistive vias-contacts a critical evaluation

Abstract

This defect-based study analyzes statistical signal delay properties and delay fault test pattern constraints in the CMOS deep submicron environment. Delay fault testing has uncertainty, or noise, in its attempt to detect defects that slow a signal. CMOS resistive vias and contacts were used as a delay defect target. Data were taken from a scan-based test chip (Veqtor) on the Philips 0.25 /spl mu/m technology. Methods to improve delay fault defect detection are given.