IEEE Journal of Solid-State Circuits · 1998 · 95 citations · 6 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated Circuit DesignIntegrated Circuit DesignPower ManagementVoltage RegulatorsVoltage ScalingCmos Analog Integrated CircuitsIntegrated Voltage Regulator DesignLow-power Cmos DesignOutput Voltage RegulationPower-down ModesVoltageVoltage Scaling For Process VariationVoltage Scaling In Digital Circuits
A fully integrated 5 V-to-3.3 V supply voltage regulator for application in digital IC's has been designed in a 3.3 V 0.5 /spl mu/m CMOS process. The regulator is able to deliver peak current transients of 300 mA, while the output voltage remains within a margin of 10% around the nominal value. The circuit draw's a static quiescent current of 750 /spl mu/A during normal operation, and includes a power-down mode with only 10 /spl mu/A current consumption. The die area is 1 mm/sup 2/, and can be scaled proportional to the maximum peak current. Special precautions have been taken to allow 5 V in the 3.3 V process.
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Circuit techniques for a VLSI memory
T. Mano, J. Yamada, Junpei Inoue et al. · IEEE Journal of Solid-State Circuits · 1983 · 33 citations
Engineering, Computer Engineering, Electrical Engineering +17
An experimental 4-Mbit CMOS DRAM
T. Furuyama, Takashi Ohsawa, Yoshihiro Watanabe et al. · IEEE Journal of Solid-State Circuits · 1986 · 28 citations
Engineering, Computer Engineering, Electrical Engineering +17