High resolution I/sub DDQ/ characterization and testing-practical issues

Abstract

I/sub DDQ/ testing has become an important contributor to quality improvement of CMOS ICs. This paper describes high resolution I/sub DDQ/ characterization and testing (from the sub-nA to /spl mu/A level) and outlines test hardware and software issues. The physical basis of I/sub DDQ/ is discussed. Methods for statistical analysis of I/sub DDQ/ data are examined, as interpretation of the data is often as important as the measurement itself. Applications of these methods to set reasonable test limits for detecting defective product are demonstrated.