Single-event gate-rupture in power MOSFETs: prediction of breakdown biases and evaluation of oxide thickness dependence

Abstract

Single-Event Gate-Rupture (SEGR) in Vertical Double Diffused Metal-Oxide Semiconductor (VDMOS) power transistors exposed to a given heavy ion LET occurs at a critical gate bias that depends on the applied drain bias. A method of predicting the critical gate bias for non-zero drain biases is presented. The method requires as input the critical gate bias vs. LET for V/sub DS/=0V. The method also predicts SEGR sensitivity to improve for larger gate-oxide thicknesses. All predictions show agreement with experimental test data.