Effects of Grain Boundaries, Field-Dependent Mobility, and Interface Trap States on the Electrical Characteristics of Pentacene TFT

Abstract

We have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results. We have set up a model considering the polycrystalline nature of pentacene and the presence of grains and grain boundaries. We show how this model can be applied to different devices with different grain sizes and we analyze the relationship between mobility, grain size and applied gate voltage. On the basis of the simulation results, we can introduce an effective carrier mobility, which accounts for grain-related effects. The comparison between experimental results and simulations allows us to clearly understand the differences in the mobility derived by the analysis of current-voltage curve (as done experimentally by using standard MOSFET theory) and the intrinsic mobility of the organic layer. The effect of the pentacene/oxide interface traps and fixed surface charges has also been considered. The dependence of the threshold voltage on the density and energy level of the trap states has been outlined.