Impact of Negative Bias Temperature Instabilities on Lifetime in p-channel Power VDMOSFETs

Abstract

Negative bias temperature instabilities (NBTI) are commonly observed in p-channel metal-oxide-semiconductor (MOS) devices when exposed to negative gate voltages at elevated temperatures. We present a brief overview of NBT stress- induced threshold voltage instabilities in p-channel vertical double-diffused MOS field-effect transistors (VDMOSFETs). NBT stress-induced threshold voltage shifts are fitted using different models to estimate the device lifetime and to discuss the impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection. The stretched exponential equation is found to provide excellent fit to experimental data for the later stress phases and thus allows an accurate estimation of device lifetime for the lowest stress voltage applied, which justifies the use of this or some other suitable fitting equation. The realistic failure criterion for devices and experimental conditions used in our studies is found to fall in the 100 - 150 mV range. The lifetime estimates are found to strongly depend on the model used for extrapolation to normal operating conditions. The 1/V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> model is shown to provide much faster output since it appears to allow the use of higher stress voltages while still yielding rather accurate lifetime estimates. Intermittent annealing does not seem to have any significant impact on device lifetime.