IEEE Circuits and Systems Magazine · 2003 · 90 citations · 54 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignIntegrated Circuit DesignInterconnect DesignInterconnect TechnologyNoise In Electronic DevicesNoise In Semiconductor DevicesPhysical DesignDesign AbstractionIntegrated Circuit NoiseInterconnect ModelingInterconnect NoiseInterconnect OptimizationNoise Analysis In Integrated CircuitsNoise ImmunityNoise In Integrated Circuits
The migration to using ultra deep submicron (UDSM) process, 0.25 μm or below, necessitates new design methodologies and EDA tools to address the new design challenges. One of the main challenges is noise. All different types of deep submicron such as cross talk, leakage, supply noise and process variations are obstacles in the way of achieving the desired level of noise immunity without giving up the improvement achieved in performance and energy efficiency. This article describes research directions and various levels of design abstraction to handle the interconnect challenges. These directions include approaches to adopt new analytical methods for interconnects, physical design levels and finally ways to face these challenges early in a higher level of the design process.
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