2002 · 113 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSystem-on-chip DesignVlsi DesignClock Distribution NetworksClock ManagementDelay ModelingIntegrated Circuit DesignTiming AnalysisTiming ModelingClock DistributionClock Distribution DesignClock Network ArchitectureClock Network ModelingLow-power Clock Network DesignMeasurement TechniquesOn-chip Transmission LinesTransmission Line Effects
Clock distribution has become an increasingly challenging problem for VLSI designs, consuming an increasing fraction of resources such as wiring, power, and design time. Unwanted differences or uncertainties in clock network delays degrade performance or cause functional errors. Three dramatically different strategies being used in the VLSI industry to address these challenges are compared. Novel modeling and measurement techniques are used to investigate on-chip transmission-line effects that are important for high performance clock distribution networks.
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Full copper wiring in a sub-0.25 μm CMOS ULSI technology
D. Edelstein, J. Heidenreich, R. Goldblatt et al. · 2002 · 352 citations
Engineering, Computer Engineering, Electrical Engineering +17
A 600 MHz superscalar RISC microprocessor with out-of-order execution
B. Gieseke, R. Allmon, Dan Bailey et al. · 2002 · 174 citations