Clock Network Modeling is a computational abstraction that represents the physical and electrical characteristics of clock distribution networks to enable accurate prediction and analysis of timing behavior, skew, and signal integrity in synchronous digital systems.
138
Publications
5.2K
Citations
369
Authors
155
Institutions
Publications per year
2017–2026
5
Parents
Publications
138
A clock distribution network for microprocessors
P.J. Restle, T. G. McNamara, Daniel Webber et al. · IEEE Journal of Solid-State Circuits · 2001 · 302 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 138
Authors
369
- EG
6
h-index
- PR
6
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- VZ
4
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- CJ
4
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- RP
4
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1–5 of 369
Institutions
155
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
6 h-index
14 publications
1.3K citations
University of Rochester
Rochester, United States
6 h-index
11 publications
1.7K citations
IBM (United States)
Armonk, United States
5 h-index
25 publications
3.5K citations
IBM Research - Austin
Austin, United States
5 h-index
16 publications
2.2K citations
University of California, Santa Cruz
Santa Cruz, United States
4 h-index
8 publications
346 citations
Synopsys (United States)
Mountain View, United States
4 h-index
6 publications
310 citations
Motorola (United States)
Schaumburg, United States
4 h-index
10 publications
209 citations
Universidade de São Paulo
São Paulo, Brazil
4 h-index
11 publications
184 citations
1–8 of 155
Venues
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
6 publications · 423 citations
6
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- IEEE Journal of Solid-State Circuits
6 publications · 553 citations
6
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- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
4 publications · 160 citations
4
h-index
- IEEE Transactions on Communications
3 publications · 88 citations
3
h-index
- Bell System Technical Journal
BSTJ · 2 publications · 29 citations
2
h-index
1–5