J.L. Sonntag

An adaptive pam-4 5-Gb/s backplane transceiver in 0.25-μm CMOS

J.T. Stonick, Gu-Yeon Wei, J.L. Sonntag et al. · IEEE Journal of Solid-State Circuits · 2003 · 133 citations

Wireless Communications, Typical Fr-4 Backplanes, Engineering +10

A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links

J.L. Sonntag, J.T. Stonick · IEEE Journal of Solid-State Circuits · 2006 · 128 citations

Engineering, Analog Design, General Architecture +16

A high speed, low power PRML read channel device

J.L. Sonntag, O.E. Agazzi, P.M. Aziz et al. · IEEE Transactions on Magnetics · 1995 · 47 citations

Low-power Electronics, Electrical Engineering, Maximum Likelihood Detection +15

A multigigabit backplane transceiver core in 0.13-/spl mu/m CMOS with a power-efficient equalization architecture

D.A. Yokoyama-Martin, A. Caffee, Curtis G. Jones et al. · IEEE Journal of Solid-State Circuits · 2005 · 43 citations

Low-power Electronics, Cascode Structure, Electrical Engineering +14

A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

J.L. Sonntag, R.H. Leonowich · 1990 · 32 citations

Electrical Engineering, Monolithic Cmos 10, Engineering +14