Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2006 · 55 citations · 5 references
EngineeringComputer ScienceManufacturing EngineeringDigital FabricationProcess ValidationSimulation-based DesignDevice ModelingDevice SimulationManufacturing SimulationPhysical DesignHotspot DetectionParameter CalibrationProcess Variation AnalysisProcess Variation Characterization
As advanced technologies in wafer manufacturing push patterning processes toward lower-k<sub>1</sub> subwavelength printing, lithography for mass production potentially suffers from decreased patterning fidelity. This results in generation of many <i>hotspots</i>, which are actual device patterns with relatively large CD and image errors with respect to on-wafer targets. Hotspots can be formed under a variety of conditions such as the original design being unfriendly to the RET that is applied, unanticipated pattern combinations in rule-based OPC, or inaccuracies in model-based OPC. When these hotspots fall on locations that are critical to the electrical performance of a device, device performance and parametric yield can be significantly degraded. Previous rule-based hotspot detection methods suffer from long runtimes for complicated patterns. Also, the model generation process that captures process variation within simulation-based approaches brings significant overheads in terms of validation, measurement and parameter calibration. In this paper, we first describe a novel detection algorithm for hotspots induced by lithographic uncertainty. Our goal is to rapidly detect all lithographic hotspots without significant accuracy degradation. In other words, we propose a filtering method: as long as there are no "false negatives", i.e., we successfully have a superset of actual hotspots, then our method can dramatically reduce the layout area for golden hotspot analysis. The first step of our hotspot detection algorithm is to build a <i>layout graph</i> which reflects pattern-related CD variation. Given a layout <i>L</i>, the <i>layout graph G =</i> (<i>V</i>, <i>E<sub>c</sub></i> union <i>E<sub>p</sub></i>) consists of nodes <i>V</i>, corner edges <i>E<sub>c</sub></i> and proximity edges <i>E<sub>p</sub></i>. A face in the layout graph includes several close features and the edges between them. Edge weight can be calculated from a traditional 2-D model or a lookup table. We then apply a three-level hotspot detection: (1) edge-level detection finds the hotspot caused by two close features or "<i>L</i>-shaped" features; (2) face-level detection finds the pattern-related hotspots which span several close features; and (3) merged-face-level detection finds hotspots with more complex patterns. To find the merged faces which capture the pattern-related hotspots, we propose to convert the layout into a planar graph <i>G</i>. We then construct its dual graph <i>G<sup>D</sup></i> and sort the dual nodes according to their weights. We merge the sorted dual nodes (i.e., the faces in <i>G</i>) that share a given feature, in sequence. We have tested our flow on several industry testcases. The experimental results show that our method is promising: for a 90nm metal layer with 17 hotspots detected by commercial optical rule check (ORC) tools, our method can detect all of them while the overall runtime improvement is more than 287X.
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Optimized hardware and software for fast full-chip simulation
Yu Cao, Yen‐Wen Lu, Luoqi Chen et al. · Optical Microlithography XVIII · 2005 · 26 citations
Chul‐Hong Park, Yoo-Hyon Kim, Ji-Soong Park et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1999 · 14 citations
Full-chip Process Simulation for Silicon DRC
Nicolas B. Cobb, Yuri Granik, Emile Sahouria et al. · TechConnect Briefs · 2000 · 12 citations
Engineering, Computer Engineering, Electrical Engineering +17