IEEE Journal of Solid-State Circuits · 1981 · 12 citations · 5 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignTiming AnalysisCycle TimeDie DesignHigh-speed Cmos DesignLow-power Cmos DesignMemory Circuit DesignSense Amplifier DesignStatic Random-access Memory DesignTwo-stage Amplifier Design
A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell size of 36/spl times/36 /spl mu/m, the die size of 3.11/spl times/4.07 mm, and the typical read access and cycle time of 18 ns are achieved. The active and standby power dissipation are 200 mW and 50 /spl mu/W, respectively.
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A high-speed, low-power Hi-CMOS 4K static RAM
T. Masuhara, O. Minato, Takeshi Sasaki et al. · 1978 · 33 citations
Engineering, Computer Engineering, Electrical Engineering +14
R. Jecmen, Alexander Ebel, Richard J. Smith et al. · 1979 · 20 citations
Engineering, Computer Engineering, Electrical Engineering +16
O. Minato, T. Masuhara, Takeshi Sasaki et al. · 1981 · 18 citations
Engineering, Computer Engineering, Electrical Engineering +13
K. Yu, R. Chwang, M. Bohr et al. · 1981 · 11 citations
Engineering, Computer Engineering, Electrical Engineering +12