Metrology needs for through-silicon via fabrication

Abstract

This paper focuses on the metrology needs and challenges of through-silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper chemical mechanical planarization. These TSVs, with typical dimensions within a factor of two or so of ≈5 μm ×50 μm (diameter×depth ), present an innovative set of metrology challenges because of the high aspect ratio and large feature sizes. The metallization deposition process includes thin layers of L/B/S metal; metrology for these layers determines whether there is complete coverage of the sidewalls. Metrology for the fill step includes verifying that the TSVs are deposited without voids and that the extent of stress on the surrounding silicon does not exceed acceptable limits.