IEEE Journal of Solid-State Circuits · 2010 · 37 citations · 15 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignMetal-oxide-semiconductor Field-effect TransistorsComplementary Metal-oxide-semiconductor DesignLow-voltage Cmos DesignRail Clamp DesignTransient DetectionTransient Event DetectionTransient NoiseTransient Noise ReductionTransient Noise Suppression
The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
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