2002 · 16 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringEmbedded SystemsMicroelectronicsSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityEmbedded DebuggingHardware DebuggingInstruction Set ArchitectureBoundary Scan DebuggingDebug Core DesignDebugging Support In System-on-chip DevicesEmbedded TestabilityLogic Built-in Self-testOn-chip DebuggingSilicon DebuggingTestability
The IEEE Std 1149.1 features have been essential in system and chip debug, test and manufacturing of UltraSPARC-III product. Several key testability features were achieved by adding a suite of customized instructions and logic to the chip core and I/Os to allow test and debug when in test mode or debug during normal operations. In addition, due to the design of high speed I/Os, extra logic was added to Boundary-Scan to maintain compliancy and provide support for all test and debug features. This paper discusses the above features and their logic implementations.
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A CMOS low-voltage-swing transmission-line transceiver
B. Gunning, L. Yuan, T. Wong · 2003 · 86 citations
Engineering, Computer Engineering, Electrical Engineering +14
Implementation of a 3rd-generation SPARC V9 64 b microprocessor
R. Heald, K. Aingaran, C. Amir et al. · 2002 · 37 citations
UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor
G. Lauterbach, D. Greenley, Sameer Ahmed et al. · 2002 · 12 citations