Boundary Scan Debugging is a hardware-assisted debugging method that enables access to the internal nodes and interconnections of an integrated circuit through a standardized serial test protocol, distinguishing itself by leveraging the IEEE 1149.1 (JTAG) boundary scan architecture to observe and control pin-level signal behavior without requiring physical probes.
9
Publications
228
Citations
17
Authors
10
Institutions
Publications per year
2017–2026
0
Parents
Publications
9
A New Post-Silicon Debug Approach Based on Suspect Window
Jianliang Gao, Yinhe Han, Xiaowei Li · 2009 · 18 citations
Boundary-scan test: a practical approach
S.L. Hurst · Microelectronics Journal · 1994 · 18 citations
1–5 of 9
Authors
17
- BE
1
h-index
- SK
1
h-index
- XL
1
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- BV
1
h-index
- SB
1
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1–5 of 17
Institutions
10
Philips (Netherlands)
Amsterdam, The Netherlands
2 h-index
4 publications
131 citations
Institute of Computing Technology
Beijing, China
1 h-index
3 publications
54 citations
Netherlands Forensic Institute
The Hague, Netherlands
1 h-index
1 publications
93 citations
Oracle (United States)
Austin, United States
1 h-index
1 publications
16 citations
IBM (United States)
Armonk, United States
1 h-index
1 publications
12 citations
Cisco Systems (United States)
San Jose, United States
1 h-index
1 publications
12 citations
Chinese Academy of Sciences
Beijing, China
1 h-index
1 publications
18 citations
Agilent Technologies (United States)
Santa Clara, United States
1 h-index
1 publications
12 citations
1–8 of 10
Venues
- Microelectronics Journal
1 publications · 18 citations
1
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- Digital Investigation
1 publications · 93 citations
1
h-index
- Proceedings of WESCON '94
1 publications · 10 citations
1
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1–3