Integration of a 3 level Cu-SiO/sub 2/ air gap interconnect for sub 0.1 micron CMOS technologies

Abstract

Integration of three level of SiO/sub 2/ air gap has been successfully achieved in a complete CMOS copper interconnect scheme. SiO/sub 2/ air gap is demonstrated to be a reliable ultra low k for sub 0.1 /spl mu/m technologies with a well controlled dielectric constant below 2.