2006 · 42 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice CharacterizationDevice ModelingDevice ScalingIntegrated Circuit DesignMemory DevicesDevice VariabilityFin Field-effect TransistorsNoise AnalysisNoise Analysis In Integrated CircuitsNoise In Metal-oxide-semiconductor Field-effect TransistorsNoise MarginsStatic Noise MarginStatic Random-access Memory Design
Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin than resist-defined fins at VDD=1.2V. These SRAM test-cells achieve 130-nm planar-bulk comparable intra-bit-cell stochastic-mismatch and static noise margins
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