Publication | Closed Access
A 0.18 μm 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)
57
Citations
8
References
2004
Year
Unknown Venue
Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureμM 3.0Chalcogenide Alloy GstPhase Change MemoryHardware SecurityNon-volatile 64Memory DeviceMemory DevicesMb Phase-transition RamPhase-change MemoryV 64Electrical EngineeringComputer EngineeringMagnetoresistive Random-access MemoryMicroelectronicsMemory ArchitectureApplied PhysicsSemiconductor MemoryResistive Random-access Memory
A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.
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