New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

C. Fenouillet-Béranger, B. Mathieu, B. Prévitali, M.-P. Samson, N. Rambal, V. Benevent, S. Kerdilès, Jean‐Paul Barnes, D. Barge, P. Besson,

2014 · 56 citations · 0 references

Concepts

Abstract

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.