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New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI
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2014
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EngineeringVlsi DesignNew InsightsIntegrated CircuitsSemiconductor DeviceSequential 3DAdvanced Packaging (Semiconductors)Transistors StabilityElectronic PackagingSemiconductor Technology3D Ic ArchitectureElectrical EngineeringLaser Annealing PromisesComputer EngineeringSemiconductor Device FabricationMicroelectronicsHigh Performance 3DThree-dimensional Heterogeneous IntegrationVlsi ArchitectureApplied PhysicsTop Mosfet TemperatureOptoelectronics3D Integration
For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.