High-Performance and Low-Temperature-Compatible p-Channel Polycrystalline-Silicon TFTs Using Hafnium-Silicate Gate Dielectric

Abstract

In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium- silicate (HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) gate dielectric are demonstrated with low- temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> gate dielectric exhibit excellent device performance in terms of higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> current ratio, lower subthreshold swing, and lower threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) albeit with slightly higher OFF-state current. More importantly, the mobility of TFTs with HfSiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> gate dielectric is 1.7 times that of TFTs with conventional deposited-SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric.