Comprehensive Analysis of Positive and Negative Bias Temperature Instabilities in High-k/Metal Gate Stack Metal–Oxide–Silicon Field Effect Transistors with Equivalent Oxide Thickness Scaling to Sub-1 nm

Abstract

We have undertaken a comprehensive analysis of the positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) reliabilities of high-k/metal gate stacks. In the case of PBTI, electron traps constituted the main factor in drain current degradation resulting in an initial jump in threshold voltage shift due to fast transient electron traps, which depended only on stress voltage, because of the formation of positive oxygen vacancies near the cathode. However, in the case of NBTI, both interface state degradation (including interface hole traps) and hole traps in bulk HfSiON should be considered. We have clarified that the interface layer quality is related to not only the high transconductance but also the hole traps. The use of a high-quality interfacial layer, such as a wet oxide interface, represents a promising solution for the improvement of NBTI lifetime.