Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Abstract

Today, 22nm node devices are built using 193nm immersion lithography, possibly combined with double patterning techniques. Some stretch till the 16nm node is feasible here, using double, triple or even quadruple patterning. Alternatively, extreme ultra violet (EUV) lithography is showing promising results, and is considered to be the most likely option for this last mentioned device node. Electrically functional 22nm node devices are already available, where EUV lithography is used for the definition of the back-end layers. Fewer results are published on the patterning of front-end layers using EUV lithography. In this work, EUV lithography is used for the patterning development of the first four critical layers (active or fin, gate, contact and metal1) of a 16nm node 6T-SRAM cell. For the first time, front-end layers will need to be printed, with EUV, and transferred into an underlying substrate. The need for optical proximity correction is checked and characterized for all layers.