Double patterning design split implementation and validation for the 32nm node

Martin Drapeau, Vincent Wiaux, Eric Hendrickx, +2

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringElectron-beam LithographyElectronic Design AutomationComputer ArchitectureDesign Split Implementation +19

Double pattern EDA solutions for 32nm HP and beyond

George E. Bailey, Alexander Tritchkov, Jea-Woo Park, +6

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Double-patterning TechniqueEngineeringVlsi DesignElectronic Design AutomationMicroscopy +18

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A. Nackaerts, Monique Ercken, S. Demuynck, +32

EngineeringVlsi DesignNode Applications6T-sram Cell BuildSemiconductor Device +14

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

Joost Bekaert, Bart Laenens, Staf Verhaegen, +22

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringVlsi DesignElectron-beam LithographyOptic Design22-Nm Sram Cells +19

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, +7

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

Wafer ProcessingEngineeringDigital ManufacturingComputer ArchitecturePattern Transfer +19

Split and design guidelines for double patterning

Vincent Wiaux, Staf Verhaegen, Shaunee Cheng, +6

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringElectronic Design AutomationComputer ArchitecturePattern TransferComputer-aided Design +18

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

T. Vandeweyer, Johan De Backer, Janko Versluijs, +4

Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE

EngineeringElectron-beam LithographyEuv LithographyNode 6T-sram DevicePatterning Development +14

Demonstration of scaled 0.099µm<sup>2</sup> FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

A. Veloso, S. Demuynck, Monique Ercken, +46

Finfet 6T-sramEngineeringElectron-beam LithographyCell TransistorsOptoelectronic Devices +15

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274μm/sup 2/ 6t-sram cell and advanced CMOS logic circuits

Liesbeth Witters, Nadine Collaert, A. Nackaerts, +38