Staf Verhaegen

Double patterning design split implementation and validation for the 32nm node

Martin Drapeau, Vincent Wiaux, Eric Hendrickx et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 94 citations

Engineering, Electron-beam Lithography, Electronic Design Automation +21

Double pattern EDA solutions for 32nm HP and beyond

George E. Bailey, Alexander Tritchkov, Jea-Woo Park et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2007 · 78 citations

Double-patterning Technique, Engineering, Vlsi Design +20

A 0.314μm/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm node applications using 0.75NA 193nm lithography

A. Nackaerts, Monique Ercken, S. Demuynck et al. · 2005 · 22 citations

Engineering, Vlsi Design, Node Applications +16

Freeform illumination sources: an experimental study of source-mask optimization for 22-nm SRAM cells

Joost Bekaert, Bart Laenens, Staf Verhaegen et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2010 · 22 citations

Engineering, Vlsi Design, Electron-beam Lithography +21

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2008 · 21 citations

Wafer Processing, Engineering, Digital Manufacturing +21