IEEE Transactions on Nuclear Science · 2011 · 16 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingFault-tolerant SystemsField-programmable Gate ArraysDesign For TestabilityDevice ReliabilityFault InjectionFpga ArchitectureHardware Fault ToleranceRedundancy TechniquesError Rate AnalysisFault Injection In MicroprocessorsFault Tolerance MechanismsFault-tolerant ArchitectureField-programmable Gate Arrays (Fpgas)Hardware Fault InjectionHardware Reliability AnalysisTriple Modular Redundancy
We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
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