A low-impedance open-bitline array for multigigabit DRAM

Abstract

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F/sup 2/ (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-/spl mu/m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.